This invention relates to electronic testing of one or more layers of a multi-chip semiconductor package.
Many computers fabricated today make use of closely spaced multi-chip modules (MCMs) that include several components or modules, such as central processing unit (CPU), static random access memory (SRAM), volatile random access memory (DRAM), read-only memory (ROM) and other devices, connected together for testing and/or operation. This module approach arrangement may reduce the time of flight and/or decrease the amount of noise sensed at any one patch. Where a central processing unit (CPU) for a microprocessor is fabricated using an MCM approach, the CPU must be tested before final assembly to determine if the associated substrate qualifies as a xe2x80x9cknown good diexe2x80x9d (KGD). At present, this KGD testing process is expensive and complex, and the connector pins for the next interconnection level may not (yet) have all the pins required for full CPU testing. Further, in a conventional approach, a microprocessor is connected to the various system components (SRAM, DRAM, ROM, etc.), and the entire assembly is tested together, through use of signals originating in the microprocessor.
Several problems are confronted using this arrangement. First, it may be impossible to test the microprocessor and each of the other components separately, because (1) the components are connected together without a convenient means of separation and (2) the connector provided for testing cannot address some of the components directly, only through the microprocessor or another intermediate component. One result of this is that, if the system fails it can be difficult to determine which component(s) or connection(s) is responsible for the system failure. Another result is that the tests for individual components may be limited by the requirement that a test signal be directed through one or more intermediary components before the test signal is received by the component to be tested. Another result is that system failure will usually require discard of the entire system, including components whose cost is high but for which the probability of failure at the component level is relatively low.
What is needed is an approach that (1) allows electrical testing of individual computer components, (2) allows testing after the system is assembled, (3) allows one or more components to be addressed directly by a test signal, without requiring signal processing by an intermediate component, (4) allows removal of an identified (failed) component in a computer system, without requiring discard of the entire system, and (5) is flexible enough to allow permutation of the order of component assembly and alteration of the test procedure to account for changes in one or more of the components being tested.
These needs are met by the invention, which provides a method for direct electrical testing of a microprocessor and of individual computer components associated with the microprocessor, using a Pin Grad Array (PGA) or another suitable array of electrical pins that provides direct access to selected circuits within each of the microprocessor and associated components. Use of a pin array allows a selected circuit in a target component, such as a microprocessor or an SRAM, to be interrogated directly and independently of other components, for purposes of evaluating target component performance and identifying reasons for target component failure, if this occurs. Components are added and tested one at a time in order to isolate and repair causes of test failures.